4 Output (4x 4 Universes) {For new implementations please use the 8x 4U board}

In this solution, the GPIO pins are used for outputting the data. The OPi Zero must output the data with 800KHz. And the 74-series logic will take care of the WS28xx timing.

The OPi Zero is outputting:

• • Enable signal (active low)

  • Pulse, 400 KHz

  • 4-bits output data (which can also easily be 8-bits)

All GPIO's used are on Port A. This makes it easy to use a single 32-bit array for directly controlling all output bits simultaneously -> no jitter.

The output is simple:

where the buffers are initialized with:

This results in the following ENABLE, PULSE stream:

The remaining required signal is the 800 KHz CLR signal. This signal is created by using an double edge detector:

This results in the following ENABLE, PULSE, CLR stream:

Next, we need a 6.4MHz clock signal. Using a crystal oscillator:

This results in the following ENABLE, PULSE, CLR, CLOCK stream:

What we need is dividing the 1.25 us pulse into 8 time slices. With the above we can finalize that timing circuit with the 74HC161 : "Presettable synchronous 4-bit binary counter; asynchronous reset". The preset is set to 0b0000.

This results in the following stream:

There is now a 3-bit counter which starts with each pulse edge.

The appropriate T0H and T1H can now be generated with comparing the 3-bit counter with the timing values specified in the datasheet. There is no comparator used (there are relative expensive), but instead there is a 8-input multiplexer, the 74HC151.

The 8-input is set by the MCP23017. In such we can set any desired T0H and TH1.

This results in the following stream for T0H and T1H:

The output stream is an OR with the T0H and and AND with the T1H. The other input for the OR and AND are the GPIO's Port A0, A1, A2 and A3.

The circuit below shows just GPIO0. This circuit is for this solution extend to 4 OR's/AND's. Which are single 74-series chip solutions.

At the end there is the volt level-shifter driver, the 74HCT125.

Prototype